Search the part. Verify the offer.

XC7A35T-1CSG324C is an Artix-7 FPGA from AMD in a 324-ball CSG package — for programmable logic, DSP and high-speed serial designs at the lowest cost per logic cell in the 7-series. The Artix-7 family is the selection point for cost-sensitive FPGA designs: serious logic capacity and transceivers without the Kintex/Virtex price tag. Selection advice: the -1 speed grade and CSG324 package must match your timing closure and layout — speed grade and package are not interchangeable across the family. Confirm your logic utilization, I/O count and transceiver needs against the datasheet before committing. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

XC7Z020-1CLG400C is a Zynq-7000 SoC from AMD in a 400-ball CLG package — dual Arm Cortex-A9 processors tightly coupled with Artix-class programmable logic on one chip. The processor-plus-FPGA integration is the selection point: software and hardware acceleration in a single device, for embedded vision, industrial control and communications. Selection advice: the -1 speed grade and CLG400 package must match your design — Zynq devices are not interchangeable across speed grades or packages. Confirm your processing, logic and I/O requirements against the datasheet, and note the Vivado toolchain requirement. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

XC6SLX9-2TQG144C is a Spartan-6 FPGA from AMD in a 144-pin TQFP package — for cost-sensitive programmable logic designs. The TQFP package is the selection point: the rare FPGA in a hand-solderable quad flat package, for low-volume and prototype designs that cannot do BGA assembly. Selection advice: the -2 speed grade and TQG144 package must match your timing and layout — Spartan-6 is a mature family, so for new high-volume designs compare against current-generation low-cost FPGAs on price and longevity. Confirm your logic and I/O requirements against the datasheet. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

10M08SAE144C8G is a MAX 10 FPGA from Altera in a 144-pin EQFP package — a non-volatile FPGA with integrated configuration memory. Instant-on nonvolatile configuration is the selection point: no external configuration flash needed, which cuts BOM cost and board space versus SRAM-based FPGAs. Selection advice: the SAE144 package and C8G speed/grade configuration must match your design — MAX 10 devices are not interchangeable across packages. Confirm your logic utilization and I/O requirements against the datasheet. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

EP4CE22F17C8N is a Cyclone IV E FPGA from Intel FPGA in a 256-ball FBGA package — for low-cost digital logic, bridging and control-plane applications. The Cyclone IV E family is the selection point for budget FPGA designs: proven silicon at commodity pricing for glue logic, protocol bridging and display control. Selection advice: the F17 package and C8N speed/grade configuration must match your design — Cyclone IV devices are not interchangeable across packages. For new designs, compare against current-generation low-cost FPGAs on price and longevity; for existing builds, match the code exactly. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LFE5U-25F-6BG381C is an ECP5 FPGA from Lattice Semiconductor in a 381-ball CABGA package — for connectivity, control-plane and video bridging. The ECP5 is the selection point for low-cost SERDES: multi-gigabit transceivers at a price point competitors reserve for logic-only devices, for PCIe, Ethernet and display bridging. Selection advice: the -6 speed grade and BG381C package must match your timing closure and layout — ECP5 devices are not interchangeable across packages. Confirm your SERDES protocol and I/O requirements against the datasheet. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

ICE40HX1K-TQ144 is a low-power iCE40 FPGA from Lattice Semiconductor in a 144-pin TQFP package — for compact programmable logic in mobile and edge devices. Ultra-low power with the fully open-source IceStorm toolchain is the selection point: the only mainstream FPGA family supported by a complete open-source flow, plus a TQFP package for easy assembly. Selection advice: the TQ144 package must match your layout — iCE40 devices span many packages that are not interchangeable. Confirm your logic utilization against the 1K LUT capacity; this is a small FPGA by design. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LCMXO2-1200HC-4TG100C is an instant-on MachXO2 programmable logic device from Lattice Semiconductor in a 100-pin TQFP package — for board control, power sequencing and glue logic. Instant-on nonvolatile configuration is the selection point: the logic is live at power-up with no external flash, which is exactly what power-sequencing and reset-control circuits need. Selection advice: the TG100C package and -4 speed grade must match your design — MachXO2 devices are not interchangeable across packages. Confirm your I/O count and logic needs against the 1200-LUT capacity. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

ATF1504AS-10AU100 is a high-density in-system programmable CPLD from Microchip Technology (Atmel) in a 100-pin TQFP package — for glue logic, bus interfacing and legacy board support. The 5 V-tolerant CPLD architecture is the selection point: it interfaces 5 V legacy buses that modern low-voltage FPGAs cannot touch directly, which keeps it in long-life industrial designs. Selection advice: the -10 speed grade and AU100 package must match your timing and layout — CPLDs are not interchangeable across packages. For new 3.3 V-only designs, compare against current-production CPLDs; for 5 V legacy systems, match the code exactly. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

EPM240T100C5N is a MAX II CPLD from Intel FPGA (Altera) in a 100-pin TQFP package, for glue logic, interface bridging and board-management functions that do not justify a full FPGA. Its advantage is instant-on nonvolatile configuration with very low static power — the logic is live at power-up with no external configuration flash needed, which simplifies the board and the power sequence. Selection advice: the T100 denotes the TQFP-100 package and C5N the speed grade and lead-free configuration — all must match your layout and timing closure. CPLD designs are tool-chain specific (Quartus), so confirm your development environment supports the MAX II family before committing. For new designs, evaluate whether a current-production CPLD or small FPGA better fits long-term availability; for existing builds, state quantity, packing and date-code requirements in your RFQ and we reconfirm the offered lot before quotation, replying within 24 hours.

LCMXO3LF-4300C-6BG256C is a Lattice MachXO3 control PLD with 4320 LUTs and 206 user I/O in a 14x14 mm 256-ball caBGA — for board-level control where an MCU is overkill and discrete logic is not enough: power sequencing, reset distribution, I/O expansion and glue logic in servers, communications and industrial controllers. Instant-on nonvolatile configuration means the logic is live at power-up with no external flash, and the on-chip 94-kbit embedded RAM plus two PLLs handle buffering and clocking without extra chips. Selection advice: the LF code is the flash-based variant (for multi-time reprogrammable NVCM choose the L version instead); the C grade covers 0 to 85C — for industrial temperature ranges specify the I grade. At 4300 LUTs this sits mid-family — designs outgrowing the 2100-LUT codes step here before the 6900, and for hardened I2C/SPI plus MIPI bridging confirm the interface IP against the MachXO3 reference designs. Parameters verified against Lattice Semiconductor documentation and distributor listings. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LFE5U-45F-6BG256C is a Lattice ECP5 FPGA with 44K LUTs, 197 user I/O and 1.9 Mbit embedded RAM in a 14x14 mm 256-ball caBGA — for connectivity-heavy designs that need real FPGA fabric without the power budget of high-end families: industrial video cameras, small-cell basebands and embedded vision preprocessors. The 1.1V core with 40-nm low-power process keeps static draw low, while 72 DSP blocks and 108 sysMEM blocks handle filtering and buffering on-chip. Selection advice: this is the LFE5U (logic-only) variant — for SERDES-based protocols specify the LFE5UM instead, since this code has no transceivers; the -6 speed grade is the fastest commercial option. ECP5 sits between MachXO3 control PLDs and larger FPGAs — confirm your LUT, RAM and DSP utilization against the family table before committing, and for MIPI CSI-2 sensor bridging check the Lattice embedded-vision reference designs. Parameters verified against Lattice Semiconductor documentation and distributor listings. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

XC7S50-1CSGA324C is an AMD Spartan-7 FPGA with 52,160 logic cells, 120 DSP slices and 210 user I/O in a 15x15 mm 324-ball CSGA — for cost-optimized programmable logic where Artix-7 is more than the budget allows: any-to-any connectivity, sensor fusion and embedded vision in industrial, consumer and automotive designs. The 28-nm fabric with MicroBlaze soft-processor support, integrated ADC (XADC) for system monitoring, and dedicated security features covers the full control-plus-processing stack on one chip. Selection advice: the -1 speed grade is the standard commercial option — for extended temperature or faster timing closure check the -2 grade; the CSGA324 package suits dense layouts, while larger packages add I/O. AMD extends 7-series FPGA lifecycles through 2040, which matters for long-life industrial programs — confirm the exact speed grade and package against your timing closure before committing. Parameters verified against AMD documentation and distributor listings. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LFMXO5-25-8BBG256C is a MachXO5-NX secure control FPGA from Lattice Semiconductor in a 256-ball CABGA package — 24,576 LUTs (25K logic capacity), 160 user I/O, 0.95–1.05 V core supply, built on the Lattice Nexus platform. The Nexus-based architecture is the selection point: instant-on control, small 14×14 mm footprint and low static power for always-on system management, bridging and security functions. Business impact: MachXO5-NX is positioned by Lattice as the industry-first FPGA family with post-quantum cryptography readiness (CNSA 2.0), so designs built on it carry a forward-looking security story that matters to communications, industrial and data-center buyers planning multi-year programs. Heat evidence: Lattice launched the MachXO5-NX TDQ (PQC-ready) devices in October 2025 with press coverage, and demonstrated the family at OCP Global Summit (Oct 14–16, 2025) — current-generation launch heat, not a legacy tail. Selection advice: the -8 speed grade and BBG256 (CABGA-256) package must match your timing closure and layout; within MachXO5-NX, the 25K device sits mid-range — step up to the 50T only if LUT utilization or I/O count demands it. Confirm logic, I/O and security-block requirements against the Lattice datasheet. Parameters verified against Lattice Semiconductor documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

XCZU3EG-1SFVC784E is a Zynq UltraScale+ EG MPSoC from AMD in a 784-ball FCBGA package — quad Arm Cortex-A53 application processors up to 1.5 GHz, dual Cortex-R5F real-time cores, Mali-400 MP2 GPU and 154K system logic cells of 16 nm FinFET+ programmable fabric on one die. The heterogeneous integration is the selection point: application processing, real-time control, graphics and FPGA acceleration collapse into a single device, cutting BOM line items, board area and chip-to-chip interface risk versus multi-chip assemblies. Business impact: the ZU3EG is the de-facto standard silicon for AI-at-the-edge vision products, so buyers inherit a deep ecosystem of SOMs, carriers and reference software instead of starting from bare metal. The Ultra96-V2, AMD Kria K24 SOM and Digilent Genesys ZU-3EG development platforms are all built on the XCZU3EG — three independent commercial platforms on the same die, with active machine-vision, ADAS and smart-camera design activity. Selection advice: the -1 speed grade and SFVC784 package must match your design; EG means quad-A53 plus Mali GPU — if you need the hardened H.264/H.265 video codec, step up to the EV line (e.g. ZU7EV); budget Vivado and PetaLinux/EDF tooling in your schedule. Confirm PS/PL partitioning and I/O needs against the AMD datasheet. Parameters verified against AMD documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

XC7K160T-2FFG676C is a Kintex-7 FPGA from AMD in a 676-ball FCBGA package — 162,240 logic cells, 600 DSP slices, 11,700 Kb block RAM, 8 GTX transceivers at up to 12.5 Gb/s and 400 user I/O on 28 nm HPL process. The price/performance positioning is the selection point: Kintex-7 delivers roughly twice the price-performance of the prior 45 nm generation at about half the power, with PCIe Gen3 and 10 GbE-class serial connectivity that Artix-7 cannot reach and without the Virtex-7 cost premium. Business impact: AMD publicly extends 7-series FPGA and adaptive SoC availability through 2040, making the 160T a low-risk choice for industrial, broadcast and communications programs with 10-plus-year service lives. Heat evidence: Kintex-7 remains the workhorse die for 3G/4G wireless, flat-panel display and video-over-IP designs, carried by the long-lived KC705 evaluation-kit ecosystem and continuous industrial demand. Selection advice: the -2 speed grade and FFG676 package must match timing closure and layout; the 160T is the sweet spot between the 70T and 325T — size up only when DSP or transceiver count forces it. For brand-new cost-driven designs, benchmark against current low-cost families; for existing builds, match the code exactly. Confirm logic, DSP and transceiver needs against the AMD datasheet. Parameters verified against AMD documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LIFCL-40-8MG289I is a CrossLink-NX FPGA from Lattice Semiconductor in a 289-ball CSBGA package — 39K logic cells, 180 user I/O, 0.95–1.05 V supply, built on 28 nm FD-SOI Lattice Nexus technology, industrial temperature grade. The FD-SOI power profile is the selection point: up to 75% lower power than similar-class competing FPGAs, with MIPI D-PHY, PCIe and DDR interfaces aimed squarely at embedded vision bridging and sensor aggregation. Business impact: a single CrossLink-NX die can bridge, aggregate and pre-process multiple camera sensors while running edge-AI inference, replacing multi-chip sensor hubs and shrinking camera-module BOMs. Heat evidence: CrossLink-NX won the 2020 Electronics Maker Best FPGA Award, is carried by Lattice sensAI (edge AI) and mVision (embedded vision) solution stacks, and the 40K device sits on Lattice official CrossLink-NX evaluation board — sustained embedded-vision design heat. Selection advice: the -8 speed grade and MG289I (industrial CSBGA-289) must match your layout; the 40K device is the top of the CrossLink-NX line — drop to LIFCL-17 for pure bridging jobs. Verify MIPI lane count, PCIe generation and I/O banking against the Lattice datasheet. Parameters verified against Lattice Semiconductor documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

XCKU060-2FFVA1156E is a Kintex UltraScale FPGA from AMD in an 1156-ball FCBGA package — 726K system logic cells, 2,760 DSP slices, 38 Mb block RAM, 32 transceivers at up to 16.3 Gb/s and 624 user I/O on 20 nm process. The DSP-and-memory density is the selection point: class-leading DSP-slice and block-RAM ratios with ASIC-like clocking for compute-heavy DSP, wireless baseband and high-throughput imaging pipelines that mid-range 7-series devices cannot close timing on. Business impact: a single KU060 absorbs fronthaul/baseband or multi-channel video-processing chains that would otherwise split across multiple FPGAs, simplifying the signal chain and its supply base. Heat evidence: the XCKU060 is the featured device on the AMD KCU105 evaluation kit and a staple of 5G wireless infrastructure, data-center acceleration and high-end test-and-measurement designs. Selection advice: the -2 speed grade and FFVA1156 package must match your design; within Kintex UltraScale the 060 sits mid-range — the 085/115 exist for larger fabrics. Note this is 20 nm UltraScale (not 16 nm UltraScale+); for new programs, check the Kintex UltraScale+ roadmap against your lifecycle needs. Confirm transceiver, memory and I/O requirements against the AMD datasheet. Parameters verified against AMD documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LFE5U-85F-6BG756C is an ECP5 FPGA from Lattice Semiconductor in a 756-ball caBGA package — 85K LUTs (the largest ECP5), dual-channel SERDES, enhanced DSP blocks and roughly 30% lower power than competing connectivity FPGAs. The low-cost SERDES is the selection point: multi-gigabit transceivers at a price point competitors reserve for logic-only devices, for PCIe, GbE and display bridging without a premium SERDES family. Business impact: ECP5 is the only mainstream FPGA family with a mature fully open-source toolchain (Project Trellis / nextpnr), which cuts tool-license cost and de-risks long-term design maintenance for cost-sensitive programs. Heat evidence: the 85F is the community-standard die behind ULX3S and OrangeCrab open-hardware boards, and ECP5 powers shipping embedded-vision products such as 360° automotive surround-view systems — in-catalog ECP5 entries stop at 45F, so the 85F completes the range upward. Selection advice: the -6 speed grade and BG756 package must match timing and layout; pick the 85F when the in-catalog 25F/45F run out of LUTs or SERDES channels. For 5 Gb/s-class SERDES, check the ECP5-5G (LFE5UM5G) variants instead. Confirm SERDES protocol and I/O needs against the Lattice datasheet. Parameters verified against Lattice Semiconductor documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

5CEFA2F23I7 is a Cyclone V E FPGA from Altera in a 484-ball FBGA package — 25K logic elements, 2,002,944 bits of embedded RAM, 224 user I/O, 1.1 V core, industrial temperature range (-40°C to +100°C junction), factory status Active. The 28 nm low-power process is the selection point: roughly 40% lower total power and 30% lower static power than the prior generation, bringing transceiver-class features to cost-sensitive industrial designs. Business impact: Cyclone V E has been in continuous industrial production for well over a decade and remains Active, so it is a proven, low-churn choice for industrial control, communications and machine-vision programs that value supply continuity over bleeding-edge fabric. Heat evidence: the Cyclone V E family is a long-running industrial workhorse with broad reference-design and development-kit coverage, and the F23 484-ball package is its mainstream high-I/O option. Selection advice: the I7 suffix is the industrial temperature grade and F23 is the 484-ball FBGA — both must match your design; within the family, 5CEFA2 sits between the smaller 5CEFA4-entry options and the larger 5CEFA5/9 devices. If your design needs a hard processor system, look at Cyclone V SoC (5CSX/5CSE) instead of the pure-FPGA E line. Confirm logic, memory and I/O requirements against the Intel/Altera datasheet. Parameters verified against Altera documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

The 10CL010YE144I7G is an Intel Cyclone 10 LP FPGA in a 144-pin EQFP with 10,320 logic elements, 46 M9K embedded memory blocks (414 Kb), 23 DSP 18 by 18 multiplier blocks, 2 PLLs and 88 general-purpose I/Os. The low-cost, low-power fabric with 1.2 V core is aimed at high-volume I/O expansion, sensor interfacing, motor control and protocol bridging, letting designers absorb glue logic and small processors into one chip and lower total system cost. It supports Nios II soft processors and the Quartus Prime tool flow for fast development. The I7 ordering code denotes the industrial temperature grade (-40C to +100C junction) with speed grade 7, and the G suffix denotes RoHS6-compliant packaging. Selection advice: note the part is Cyclone 10 LP, not MAX 10; match the 1.2 V standard core supply (Y code) rather than the 1.0 V low-voltage Z code, and pick speed grade 6 if your design needs the fastest timing bin instead of assuming margin on grade 7. Parameters verified against Intel FPGA documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

Intel Arria 10 GX FPGA 10AX027H3F34I2SG is a 20 nm mid-range FPGA with 270K logic elements, 101,620 adaptive logic modules, 17,870,848 bits of embedded memory, 830 variable-precision DSP blocks, 24 14.2 Gbps transceivers, 384 general-purpose I/Os, two PCI Express Gen3 hard IP blocks and eight hard memory controllers in a 1152-ball FBGA package. The hard IP blocks are the efficiency gain: PCIe, memory control and transceiver PCS functions run in dedicated silicon instead of consuming fabric, so designs close timing faster, use less logic for the same throughput, and leave headroom for future features without a respin. For programs in communications, broadcast, computing and storage acceleration, that means one qualified device covers high-bandwidth I/O plus heavy DSP in a single chip, cutting BOM count, board spins and requalification cost versus a soft-IP or multi-chip approach. Evidence: the GX 270 resource counts and the 0.9 V core supply come from the Intel Arria 10 Device Overview, and the ordering code decodes exactly to this device: 027 is 270K logic elements, H is 24 transceivers, F34 is the 1152-ball FBGA, I is the industrial temperature grade (-40C to +100C junction), 2 is fabric speed grade 2, S is standard power and G is RoHS6. Selection advice: match the full ordering code character for character, because Arria 10 GX devices are not interchangeable across density, package, transceiver count or speed grade; the H3 code fixes 24 transceivers at transceiver speed grade 3, and the F34 package fixes the 1152-ball footprint and pinout, so a different suffix is a different board. If your design needs an ARM hard processor system, step to the Arria 10 SX line instead of the GX line; if it needs more than 270K logic elements, step up to the GX 320 or higher in the same family and recheck the package plan. Parameters verified against Intel FPGA documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LCMXO2-2000HC-4TG100C is an instant-on MachXO2 programmable logic device from Lattice Semiconductor in a 100-pin TQFP (14 x 14 mm) — for board control, power sequencing, reset distribution and glue logic in communications, computing and industrial equipment. Nonvolatile configuration is the selection point: the logic is live at power-up with no external boot flash, which is what sequencing and reset-control circuits need. This 2000-density code is the same-footprint step up from the LCMXO2-1200HC-4TG100C: the same 79 user I/O, but 2,112 LUTs (roughly 65% more logic), 74 kb of embedded block RAM, 16 kb of distributed RAM and 80 kb of user flash memory for parameters or boot code, plus one PLL for clock conditioning. The HC core runs from a 2.5 V or 3.3 V rail through its on-chip regulator, simplifying the power tree. Selection advice: this code is the -4 speed grade in the commercial temperature version — confirm -4 timing against your design closure, and check that 79 I/O and 2,112 LUTs cover your control functions before committing the layout, because larger MachXO2 densities change package. Parameters verified against the Lattice MachXO2 family datasheet (FPGA-DS-02056). State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LCMXO2-4000HC-4FTG256C is an instant-on MachXO2 programmable logic device from Lattice Semiconductor in a 256-ball ftBGA (17 x 17 mm, 1.0 mm pitch) — for board-level control in servers, communications and industrial systems that need more I/O and logic than the leaded packages offer. The selection point is the combination of instant-on nonvolatile configuration with 4,320 LUTs, 206 user I/O, 92 kb of embedded block RAM, 34 kb of distributed RAM, 96 kb of user flash memory and two PLLs: control logic, I/O expansion and bridging that is live at power-up with no external boot flash. The FTG256 package matters on the assembly line — its 1.0 mm ball pitch is easier to route, assemble and inspect than the finer-pitch caBGA option at the same 206 I/O count. The HC core runs from a 2.5 V or 3.3 V rail through its on-chip regulator. Selection advice: this code is the -4 speed grade in the commercial temperature version — confirm -4 timing against your closure targets, and fix the package choice early, because MachXO2 densities and packages are not interchangeable once the board is laid out. Parameters verified against the Lattice MachXO2 family datasheet (FPGA-DS-02056). State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.