PSC3M5EDLGQ1

PSC3M5EDLGQ1 is an Infineon Technologies PSOC Control C3 Main Line microcontroller for compact motor control and digital power designs, built around a 180 MHz Arm Cortex-M33 core with 128 KB Flash and 64 KB SRAM in a VQFN-48 package. It keeps the CORDIC math coprocessor and the MOTIF Hall and encoder interface of the M5 line, with a 12-bit 12 Msps SAR ADC offering 12 channels and four serial communication blocks (SCB); the 48-pin family devices do not route SCB4 and SCB5. The benefit is the Main Line control feature set in the smallest PSC3 package, for single-motor drives, compact power stages, and dense boards where 12 analog channels and four serial blocks cover the design. For buyers, the trade is explicit: choose this LG code for board area, and choose a 64-pin or 80-pin M5 code when the design needs 18 ADC channels and six serial blocks. Evidence: Infineon datasheet 002-36032 lists PSC3M5EDLGQ1 in VQFN-48 (PG-VQFN-48) with active and preferred status and a -40 °C to +115 °C operating range. Selection advice: order the full PSC3M5EDLGQ1XQLA1 code including the XQLA1 suffix, which differs from the XQSA1 suffix on earlier PSC3 listings.