SN74LVC2G126DCUR

SN74LVC2G126DCUR packs two independent bus buffers with 3-state outputs into an eight-pin VSSOP (DCU) package. The selection point is the enable polarity: unlike its SN74LVC2G125 sibling, whose output enables are active-low, the 2G126 enables are active-high, so the buffers turn on with a logic-high control signal. That single difference decides whether the part drops cleanly into a design whose gating signal is generated active-high by an FPGA or MCU, without adding an inverter gate. Electrically it is standard LVC: 1.65 V to 5.5 V operation, 5.5 V-tolerant inputs and disabled-state outputs, strong drive for short board buses, and Ioff protection so a powered-down channel does not load a live line. Typical placements are pairs of signals that need a shared disconnect — SPI chip-select conditioning, sensor buses and modular daughtercards. Selection advice: verify the OE polarity against your schematic before release, because the 2G125 and 2G126 are pin-compatible in the same VSSOP-8 footprint and an ordering mix-up produces a board whose buffers are permanently off. Order by the full DCUR code for the tape-and-reel VSSOP variant. Parameters verified against Texas Instruments documentation.