NT6CL128T64C4-H1

NT6CL128T64C4-H1 is the 256-ball PoP FBGA ordering code for a Nanya Technology 8 Gbit LPDDR3 SDRAM, written word-for-word in the ordering table of the maker's C-die datasheet: a dual-die (DDP) package stacking two 4 Gbit dies for a 128M x 64, dual-channel organization at 1866 Mb/s per pin with read latency 14. The HSUL_12 interface runs a 1.8 V core supply with 1.2 V I/O rails, which is what lets mobile and embedded SoC platforms keep DRAM power down without moving to a newer LPDDR generation. The code surfaced in an ic.net.cn buy request for 20,000 pieces on scan day, evidence of live production demand for this mature LPDDR3 step. Selection advice: the C in the code is the third-generation die revision and the H1 tail is the 1866 Mbps speed grade — do not substitute the D-die sibling codes (the NT6CL128T64DR4 form) without requalifying against your controller timing, and note this is a bare component code, not a module. Nanya publishes no discontinuation notice for the code in the material captured at verification, and the status is stated in those neutral terms. Parameters verified against Nanya Technology documentation.