PCF8574T/3,518

ARA-2120AA-CA0T-T is the commercial-grade, tray-packed orderable form of the NXP Semiconductors Ara240 discrete neural processing unit (DNPU), a dedicated AI companion accelerator delivering up to 40 equivalent TOPS (eTOPS) at a 900 MHz core frequency with support for up to 16 GB of LPDDR4 memory at a typical power consumption of 6.5 W. It offloads transformer, CNN, LLM, VLM and VLA inference from the host processor through a 4-lane PCIe Gen4 interface or USB 3.2 Gen 1, so edge systems run large models locally with low latency instead of depending on cloud compute. The business gain is measurable: local inference cuts recurring cloud cost, keeps sensitive data on device, and lets an existing host platform add generative-AI capability without a full redesign, while secure boot and a hardware root-of-trust processor harden deployment in industrial and enterprise environments. Evidence: NXP lists the Ara240 with these specifications on its official product page and publishes the commercial datasheet (Rev. 2.0, April 2026) that defines this ordering code, and the device is covered by the NXP Product Longevity program with a minimum 10-year availability. Selection and procurement advice: the DNPU is a companion accelerator, not a standalone host, so confirm host interface, lane configuration, memory size and SDK support against your platform before ordering; the trailing T denotes tray packing (B denotes bulk) and the C denotes commercial grade, so quote the full ARA-2120AA-CA0T-T code character for character, since packing and grade change the supplied part. Featured in Mouser new-product coverage dated October 5, 2026. Parameters verified against NXP Semiconductors documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

ARA-2120AA-IA0T-B is the industrial-grade, bulk-packed orderable form of the NXP Semiconductors Ara240 discrete neural processing unit (DNPU), a dedicated AI companion accelerator delivering up to 40 equivalent TOPS (eTOPS) at a 900 MHz core frequency with support for up to 16 GB of LPDDR4 memory. It offloads transformer, CNN, LLM, VLM and VLA inference from the host processor through a 4-lane PCIe Gen4 interface or USB 3.2 Gen 1, so edge systems run large models locally with low latency instead of depending on cloud compute. The business gain is measurable: local inference cuts recurring cloud cost, keeps sensitive data on device, and lets an existing host platform add generative-AI capability without a full redesign, while secure boot and a hardware root-of-trust processor harden deployment in industrial and enterprise environments. Evidence: NXP publishes the industrial datasheet (ARA240IND, Rev. 3.0, July 2026) that defines this ordering code with these specifications, and NXP Product Longevity lists the Ara240 DNPU through April 2036. Selection and procurement advice: the DNPU is a companion accelerator, not a standalone host, so confirm host interface, lane configuration, memory size and SDK support against your platform before ordering; the trailing B denotes bulk packing (T denotes tray) and the I denotes industrial grade, so quote the full ARA-2120AA-IA0T-B code character for character, since packing and grade change the supplied part; choose this industrial-grade form over the commercial CA0T forms for industrial deployment. Featured in Mouser new-product coverage dated October 5, 2026. Parameters verified against NXP Semiconductors documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

ARA-2120AA-IA0T-T is the industrial-grade, tray-packed orderable form of the NXP Semiconductors Ara240 discrete neural processing unit (DNPU), a dedicated AI companion accelerator delivering up to 40 equivalent TOPS (eTOPS) at a 900 MHz core frequency with support for up to 16 GB of LPDDR4 memory. It offloads transformer, CNN, LLM, VLM and VLA inference from the host processor through a 4-lane PCIe Gen4 interface or USB 3.2 Gen 1, so edge systems run large models locally with low latency instead of depending on cloud compute. The business gain is measurable: local inference cuts recurring cloud cost, keeps sensitive data on device, and lets an existing host platform add generative-AI capability without a full redesign, while secure boot and a hardware root-of-trust processor harden deployment in industrial and enterprise environments. Evidence: NXP publishes the industrial datasheet (ARA240IND, Rev. 3.0, July 2026) that defines this ordering code with these specifications, and NXP Product Longevity lists the Ara240 DNPU through April 2036. Selection and procurement advice: the DNPU is a companion accelerator, not a standalone host, so confirm host interface, lane configuration, memory size and SDK support against your platform before ordering; the trailing T denotes tray packing (B denotes bulk) and the I denotes industrial grade, so quote the full ARA-2120AA-IA0T-T code character for character, since packing and grade change the supplied part; choose this industrial-grade form over the commercial CA0T forms for industrial deployment. Featured in Mouser new-product coverage dated October 5, 2026. Parameters verified against NXP Semiconductors documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LPC1768FBD100 is an NXP Semiconductors Arm Cortex-M3 microcontroller in LQFP-100 — for Ethernet-connected embedded designs: industrial gateways, access control and instrumentation. The on-chip Ethernet MAC plus USB and CAN is the selection point: full connectivity without external controllers. Selection advice: the FBD100 denotes LQFP-100 — confirm your network stack (e.g., lwIP) fits the 512 KB Flash / 64 KB SRAM; for new designs, compare NXP's newer i.MX RT crossover MCUs for more headroom. A mature line with long availability. Parameters verified against the NXP official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

LPC55S69JBD100 is an NXP dual-core ARM Cortex-M33 microcontroller at 150 MHz — 640 KB Flash, 320 KB SRAM in 100-pin HLQFP. The selection point is security plus DSP: ARM TrustZone, AES-256/SHA-2 crypto accelerators, secure boot, and a PowerQuad DSP coprocessor for motor control and audio front-ends. Selection advice: the JBD100 code is the 100-pin HLQFP — for 64-pin designs the JBD64 is the smaller twin, and the JEV98 VFBGA suits space-constrained boards. The S69 is the full-feature variant; the S66 drops the second core for cost-sensitive designs — match the security and DSP requirements before substituting. Parameters verified against NXP documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

MIMXRT1062DVL6A is an NXP i.MX RT1062 crossover MCU — for industrial HMI, motor control and edge audio where a classic MCU runs out of headroom but an applications processor is overkill: 600 MHz Arm Cortex-M7, 1 MB on-chip SRAM, and LCD/camera/audio interfaces in a 12x12 mm 196-ball MAPBGA. The crossover architecture pairs MCU real-time determinism with MPU-class performance — 3015 CoreMark — plus 2D graphics acceleration and PDM microphone inputs for voice UIs. Selection advice: the DVL6A code is the 196 MAPBGA — for cost-optimized 2-layer boards the LQFP variants of the RT1010/RT1020 family are the step down; the RT1064 adds on-chip flash for XiP-free designs. NXP guarantees long-term availability through its Product Longevity Program — confirm the silicon revision against your SDK version before committing. Parameters verified against NXP documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

MIMXRT1176DVMAA is NXP's flagship i.MX RT1170 crossover MCU: a 1 GHz Arm Cortex-M7 paired with a 400 MHz Cortex-M4 and 2 MB on-chip SRAM in a 289-pin LFBGA, with 3x CAN FD, 3x Ethernet and 2x USB. The dual-core split is the business case — the M7 runs the application and display stack while the M4 handles real-time control on the same die, removing a second MCU from high-end HMI, industrial-controller and gateway BOMs, and the large on-chip SRAM cuts external SDRAM out of many designs. Heat evidence: NXP positions the RT1170 as its highest-performance crossover MCU; it succeeds the widely adopted RT1062 (already carried in this catalog), and the MIMXRT1170-EVK evaluation ecosystem is broadly used for HMI and industrial control development. Selection advice: the DVMAA suffix pins the 1 GHz speed grade and LFBGA-289 package — lower speed grades and alternate BGA variants are not interchangeable, so match the full orderable character-for-character; verify display, Ethernet PHY and pin-multiplexing requirements against the datasheet, since this package is densely multiplexed. Parameters verified against NXP documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC138D,653 is a Nexperia 3-to-8 line decoder/demultiplexer with inverting outputs in SO-16 — for address decoding: chip-select generation, LED multiplexing and bus demultiplexing. Three address lines selecting eight outputs is the selection point: decoding logic without MCU pins. Selection advice: the D,653 suffix denotes SO-16 — pick the 138 for active-low chip selects (the most common); the 12 ns propagation delay suits most glue-logic timing. For active-high outputs, the 74HC238 is the sibling. Nexperia lists this part as Active. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC595D,118 is a Nexperia 8-bit shift register with output latch and 3-state outputs in SO-16, reel — for expanding MCU outputs: LED matrices, relay banks and 7-segment displays. Three pins driving unlimited cascaded outputs is the selection point: GPIO expansion at cents per pin. Selection advice: the D,118 suffix denotes SO-16 in reel for production — a second source to TI's SN74HC595D for supply resilience; verify logic thresholds match your design if mixing vendors. For tighter spaces, the TSSOP PW,118 variant shrinks the footprint. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC595S16-13 is a Diodes Incorporated 8-bit shift register with 8-bit output register in SO-16, 13-inch tape and reel — for expanding MCU outputs: LED matrices, relay banks and 7-segment displays. Three pins driving unlimited cascaded outputs is the selection point: GPIO expansion at cents per pin. Selection advice: the S16-13 suffix denotes SO-16 on 13-inch reel for production — a second source to TI's SN74HC595D and Nexperia's 74HC595D for supply resilience; 2.0 V to 6.0 V supply with push-pull outputs covers most logic designs. Parameters verified against the Diodes official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.