ICE40UP5K-SG48I

iCE40UP5K-SG48I is a low-power iCE40 UltraPlus FPGA from Lattice Semiconductor in a 48-pin QFN (7 x 7 mm, 0.5 mm pitch) — a low-density device in its own right, ordered under this complete code, for always-on sensing, sensor aggregation and portable or battery-powered edge products. The selection point is what is hardened on the die: 5,280 logic cells, 30 embedded RAM blocks (120 Kb), four single-port RAM blocks totalling 1,024 Kb for frame and data buffering, eight DSP blocks with 16-bit multipliers and 32-bit accumulators, one PLL, and hardened I2C (x2) and SPI (x2) blocks that keep the fabric free for custom logic — all on a 1.2 V core with nonvolatile configuration memory. This SG48I code is the industrial-grade version in the QFN-48 package, which gives the device its maximum 39 user I/O; smaller packages expose fewer pins. Selection advice: choose SG48 when your design needs those 39 I/O and can accept the 7 x 7 mm footprint — the ultra-small wafer-level options trade I/O count for size. Note for assembly: the QFN paddle must be connected to GND. Parameters verified against the Lattice iCE40 UltraPlus family datasheet (FPGA-DS-02008).