74HC574PW

74AVC9112DCH is a 1:4 clock fanout buffer from Nexperia in VSSOP-8 — for distributing one clock to four loads with low skew in digital systems. The 1:4 fanout is the selection point: one device replaces four discrete buffers, keeping clock edges aligned across loads. Selection advice: the AVC family runs at low voltage for modern logic levels — confirm your clock voltage and frequency fit the device ratings before committing. The DCH suffix denotes VSSOP-8. For more outputs, look at larger fanout buffers in the same family. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC04D,653 is a Nexperia hex inverter in SO-14 — for basic logic inversion: signal polarity fixes, clock inversion and simple glue logic. Six inverters in one package is the selection point: a low-cost way to fix polarity mistakes on a finished board. Selection advice: the D,653 suffix denotes SO-14 — pick the 74HC04 for plain inversion; when the input is slow or noisy, the Schmitt-trigger 74HC14 is the safer choice. 2.0–6.0 V supply covers most logic designs. Nexperia lists this part as Active. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC08D,653 is a Nexperia quad 2-input AND gate in SO-14 — for basic combinational logic: gating clocks, combining enables and simple glue logic. Four AND gates with 7 ns propagation delay is the selection point: fast-enough combining logic at the lowest cost. Selection advice: the D,653 suffix denotes SO-14 — pick the 74HC08 for plain AND logic; for wider functions in one package, consider multi-function gates. 2.0–6.0 V supply covers most logic designs. Nexperia lists this part as Active. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC138D,653 is a Nexperia 3-to-8 line decoder/demultiplexer with inverting outputs in SO-16 — for address decoding: chip-select generation, LED multiplexing and bus demultiplexing. Three address lines selecting eight outputs is the selection point: decoding logic without MCU pins. Selection advice: the D,653 suffix denotes SO-16 — pick the 138 for active-low chip selects (the most common); the 12 ns propagation delay suits most glue-logic timing. For active-high outputs, the 74HC238 is the sibling. Nexperia lists this part as Active. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC14D,653 is a Nexperia hex inverting Schmitt trigger in SO-14 — for cleaning up noisy signals: button debouncing, slow-edge squaring and simple oscillators. The Schmitt hysteresis is the selection point: reliable switching on slow or noisy inputs where plain inverters chatter. Selection advice: the D,653 suffix denotes SO-14 — pick the 74HC14 for debouncing and signal conditioning; one gate plus an RC makes a simple clock oscillator. For non-inverting hysteresis, the 74HC14's sibling 74HC7014 (where available) is the alternative. Nexperia lists this part as Active. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC595D,118 is a Nexperia 8-bit shift register with output latch and 3-state outputs in SO-16, reel — for expanding MCU outputs: LED matrices, relay banks and 7-segment displays. Three pins driving unlimited cascaded outputs is the selection point: GPIO expansion at cents per pin. Selection advice: the D,118 suffix denotes SO-16 in reel for production — a second source to TI's SN74HC595D for supply resilience; verify logic thresholds match your design if mixing vendors. For tighter spaces, the TSSOP PW,118 variant shrinks the footprint. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC595PW,118 is a Nexperia PRODUCTION 8-bit serial-in, serial or parallel-out shift register with output latches and 3-state outputs in TSSOP-16 — for expanding MCU outputs in tight spaces: LED matrices, relay banks and display drivers. Three pins driving unlimited cascaded outputs is the selection point: GPIO expansion at cents per pin. Selection advice: the PW,118 suffix denotes TSSOP-16 — the compact variant of the SO-16 D,118; 2.0 V to 6.0 V supply and up to 108 MHz clock cover most logic designs. A second source to TI's SN74HC595PW for supply resilience. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

74HC74D,653 is a Nexperia dual D-type flip-flop with set and reset, positive-edge triggered, in SO-14 — for divide-by-two counters, data synchronization and toggle circuits. Independent set/reset on each flip-flop is the selection point: flexible state control without extra gates. Selection advice: the D,653 suffix denotes SO-14 — pick the 74HC74 for classic dual flip-flop duty; for single-gate fixes, the 1G/2G little-logic families save board space. 82 MHz max frequency covers most glue-logic clocking. Nexperia lists this part as Active. Parameters verified against the Nexperia official product page. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

CH32V003F4P6 is a 32-bit RISC-V MCU from WCH — 48 MHz, 16 KB Flash, 2 KB SRAM, 10-bit ADC, in a 20-pin TSSOP package. The RISC-V open architecture at an 8-bit price point is the selection point: 32-bit performance for the cost of a legacy 8-bit MCU, which is why the CH32V003 became the default for cost-driven control tasks. Selection advice: the F4P6 suffix denotes this Flash size and the TSSOP-20 package — match the full code to your layout. The RISC-V toolchain differs from ARM: confirm your development environment supports the WCH RISC-V core before committing. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.

PCM5102A is a Texas Instruments 112-dB SNR stereo audio DAC in 20-pin TSSOP — for network streamers, USB DACs and smart-speaker line outputs where clean analog must come from I2S with minimal support circuitry: 32-bit, up to 384-kHz sampling, integrated PLL generates the system clock from BCLK (3-wire I2S, no MCLK), and DirectPath 2.1-VRMS ground-centered outputs eliminate DC-blocking capacitors. Selection advice: the hardware-pin-controlled A variant suits fixed-function designs — for software-controlled filtering choose the PCM5122; against the automotive PCM5102A-Q1 on this site, the catalog grade covers -25 to +85C commercial/industrial use. Up to 20-dB lower out-of-band noise than conventional switched-capacitor DACs eases downstream amplifier/ADC filtering. Parameters verified against Texas Instruments documentation. State quantity, packing and date-code requirements in your RFQ; we reconfirm the offered lot before quotation and reply within 24 hours.