PSC3M5EDACQ1

PSC3M5EDACQ1 is an Infineon Technologies PSOC Control C3 Main Line microcontroller for motor control and digital power, built around a 180 MHz Arm Cortex-M33 core with 128 KB Flash and 64 KB SRAM in an E-LQFP-64 package. It keeps the full Main Line M5 analog and interface set: a 12-bit 12 Msps SAR ADC with 18 channels, a CORDIC math coprocessor, the MOTIF Hall and encoder interface, and six serial communication blocks (SCB). The benefit is the same control-loop performance as the 256 KB M5 in the same 64-pin leaded package, sized for designs whose firmware fits 128 KB: the fast ADC and hardware math keep field-oriented control responsive without paying for memory the application does not use. For buyers, the ED code is the 128 KB choice within the M5 line; note that PSA L2 security applies to the 256 KB devices, not this one, so step up to the FDS2 code if PSA L2 is a program requirement. Evidence: Infineon datasheet 002-36032 lists PSC3M5EDACQ1 in E-LQFP-64 with active and preferred status and a -40 °C to +115 °C operating range. Selection advice: order the full PSC3M5EDACQ1XQLA1 code including the XQLA1 suffix, which differs from the XQSA1 suffix on earlier PSC3 listings.