PSC3P8GFS3PACQ1

PSC3P8GFS3PACQ1 is a PSOC Control C3 Performance Line microcontroller from Infineon Technologies for high-frequency digital power conversion, built around a 180 MHz Arm Cortex-M33 main core plus a programmable power control accelerator (PPCA) with two 200 MHz Cortex-M33 cores, with 512 KB Flash, 128 KB SRAM, four 12-bit 25 Msps SAR ADCs, 26-channel TCPWM including 12-channel high-resolution PWM with sub-100 ps resolution, two CAN FD channels, and CryptoLite security in a 64-pin E-LQFP package. The PPCA is the selection point: it closes control loops inside dedicated hardware instead of loading the main core, so designs hold tight regulation at switching frequencies up to 2 MHz with wide-bandgap GaN or SiC switches, which is how AI server PSUs, solar inverters, EV chargers, and high-density SMPS reach higher efficiency and power density without a larger controller. The business gain is a smaller, cooler power stage: fewer external control parts, faster transient response, and one qualified MCU platform across power tiers. Evidence: Infineon lists this ordering code as NEW on its PSOC Control C3 Performance Line page with Sept 2026 availability, 512 KB Flash, 128 KB SRAM, 33 GPIO, and a -40 C to +115 C operating range, and the Performance Line family documentation defines its PPCA, ADC, and PWM configuration. Selection advice: choose the P8 power-conversion variant over the M8 motor variant when the design is a converter rather than a drive; choose this 64-pin E-LQFP form when 33 GPIO cover the design and board space matters most, since it is not pin-compatible with the 80-pin and 100-pin forms; match the full PSC3P8GFS3PACQ1 code, because the C3 family spans Entry, Main, and Performance lines that are not drop-in interchangeable. Infineon marks this code NEW with Sept 2026 availability. Parameters verified against Infineon Technologies documentation.