PSC3M6FDS2AFQ1

The PSC3M6FDS2AFQ1 is a motor-control member of the Infineon PSOC Control C3 family in an E-LQFP-80 package, built on a 180 MHz Arm Cortex-M33 core with DSP, FPU and a CORDIC accelerator, rated from -40 to +115 degrees C. It provides 256 KB of flash, 64 KB of SRAM, a 24-channel ADC, 54 GPIO and PSA Level 2 security. Its distinguishing point: the mid-size package keeps all 24 ADC channels, where the 64-pin family codes drop to 19, preserving the full analog front end for phase-current and bus-voltage sampling in a smaller footprint, suiting compact drives for pumps, fans and appliance motors. Selection advice: choose this code when 24 analog channels matter more than memory headroom; step to the 512 KB PSC3M6GES3AFQ1 for larger firmware or PSA Level 3, and confirm the 80-pin footprint before layout, since it is not pin-compatible with the 64-pin or 100-pin codes. Evidence: the Infineon PSOC Control C3 product brief lists this ordering code with this configuration. Parameters verified against Infineon Technologies documentation.