TSMC Q3 Profit +69%, Q4 +55–61%: Foundry Allocation Guide

The short version

TSMC's October 15 earnings call delivered the strongest numbers in the company's history — and a message that component buyers should read differently than investors do. Q3 net income rose 68.7% year-on-year to NT$763.06 billion (roughly US$23.9 billion), revenue hit $46.72 billion, and Q4 guidance of $52.3–54.3 billion reportedly implies growth of 55–61% year-on-year. CEO C.C. Wei said AI accelerator demand shows no sign of slowdown and will probably grow faster than the already-steep mid-to-high-50% annual rate TSMC projects for 2024–2029. But two details in the same call matter more for buyers than the headline. First, Wei said consumer and price-sensitive end markets are being challenged by rising component prices and macroeconomic uncertainty. Second, the call confirmed that capacity — not demand — is the constraint: about 20 fabs are in various stages of construction or planning, 2026–2028 capex will reportedly be "significantly higher" than the prior three years, and CoWoS packaging remains sold out with lead times stretching into 2027. When capacity is the constraint, your allocation tier matters more than your price. This article explains what TSMC's numbers mean for anyone buying chips that run through a foundry — which is nearly everyone.

Semiconductor fab cleanroom with EUV lithography machine

The numbers: a foundry with no spare capacity

The Q3 figures below are from TSMC's official report, except for the brokerage forecasts for 2027 capex, which are listed separately after the official figures and are not TSMC guidance: - **Revenue:** $46.72 billion (NT$1.49 trillion), up 41.2% in USD terms year-on-year, reportedly beating TSMC's own $44.6–45.8 billion guidance. - **Net income:** NT$763.06 billion, up 68.7%. Sixth consecutive quarterly profit record. - **Gross margin:** 66.4%, down 1.3 points quarter-on-quarter — the cost of ramping 2nm. - **Q4 guidance:** $52.3–54.3 billion revenue, gross margin 65–67%, operating margin 56.5–58.5%. - **2026 outlook:** Full-year 2026 revenue growth is now guided to about 44% in USD terms. - **Capex:** Q3 capex was about $13.8 billion; 2026 guidance is $60–64 billion. 2026–2028 capex will reportedly be "significantly higher" than the prior three years. **Brokerage forecasts for 2027 capex (reported by TrendForce, not TSMC guidance):** Morgan Stanley $83 billion, Goldman Sachs and Bank of America $85 billion, and UBS $90 billion. The mix shift tells the allocation story: - **2nm** reached 8% of wafer revenue in Q3, up from 3% in Q2 — its first quarter of scale contribution. - **3nm** hit 33%, overtaking 5nm (28%) as TSMC's largest single node. 7nm contributed 10%. Advanced nodes (7nm and below) totaled 79%. - **High-performance computing** was 68% of revenue (up 22% quarter-on-quarter); smartphones were 21% of revenue (up 10% quarter-on-quarter in absolute terms). North America contributed 79% of revenue; mainland China 5% (down from 8%). Translation: the world's most important chip factory is now mostly an AI factory. Smartphone chips — the volume business that used to anchor foundry planning — are a shrinking share. If your products are not AI accelerators, you are competing for a shrinking slice of TSMC's attention.

The 2nm cost cascade: $30,000 wafers and rising

The most buyer-relevant number in the entire earnings cycle is not in the official report — it comes from supply-chain reporting, and must be labeled as such. Supply-chain reports put TSMC's 2nm wafer price at roughly **$30,000** per wafer; estimates of the premium over 3nm range from 10–20% to 50%. The increase is driven by gate-all-around transistors, EUV intensity, and early-ramp yields. And it is still rising. Reports say TSMC will raise wafer prices by roughly 3–6% from January 2027, with 2nm and 3nm seeing the largest increases (unconfirmed by TSMC). That cost flows directly into every 2nm product: Apple's A20, NVIDIA's Vera Rubin, AMD's MI400, Broadcom's custom ASICs, Qualcomm's next flagship SoC. Capacity is expanding but not fast enough to change the pricing dynamic. Per Economic Daily News (via TrendForce), TSMC targets 2nm capacity growth of 22% (from ~90,000 to ~110,000 wafers/month) and 3nm growth of 16%+ (from ~180,000 to ~210,000) from end-2026 to mid-2027. TSMC projects roughly 70% compound annual growth in 2nm capacity from 2026 through 2028. But demand is growing faster: customers including Apple, NVIDIA, AMD, Qualcomm, and MediaTek have reportedly increased 2nm orders by 10–20%.

The two messages: "no slowdown" vs. "cautious on 2027"

Wei's call contained two messages that sound contradictory. They are not — they describe different things. **"No sign of slowdown"** is about *demand*. AI accelerator orders keep rising; customers keep raising their forecasts. The demand-supply gap remains "quite big," in Wei's words. TSMC's ~20 fabs in various stages of construction or planning worldwide are a response to demand that already exists. **"Cautious on 2027"** is about *planning under uncertainty*. Wei pointed to consumer and price-sensitive segments being challenged by rising component prices and macroeconomic uncertainty. Tool, material, and labor inflation is real (CFO Wendell Huang confirmed it). Overseas fab dilution is reportedly ~2% this year, widening to 3–4% in later years as more US fabs ramp. For buyers, the split resolves into a simple rule: **demand is certain, supply timing is not.** Plan as if AI demand stays strong (because TSMC's customers say it will) but as if your specific allocation could slip (because TSMC won't commit to 2027 capacity numbers yet). That means earlier commitments, not later ones.

The packaging signal: Wei offers to be the backup

The most revealing moment of the call had nothing to do with earnings. Asked whether TSMC would supply customers who chose Intel's EMIB-T packaging and then could not get enough of it, Wei said: "I try to avoid answering it directly, but let me say that, yes, we will be" — adding that TSMC's first priority is that a customer's "product can be introduced into the market smoothly." Intel shares fell more than 5% that day. Read this as a buyer, not an investor. TSMC is publicly positioning itself as the fallback for the entire industry's advanced packaging. That only makes sense if TSMC believes packaging capacity — CoWoS especially — will remain the binding constraint and that competitors' alternatives will fall short. It connects directly to our earlier reporting: CoWoS is sold out through the end of the year with lead times into 2027, and TSMC's $2 billion GlobalFoundries interposer deal exists precisely because in-house capacity is insufficient. The same logic extends to the secondary market. Asked about customers reselling allocation, TSMC reportedly said customers may not sublet or auction capacity (limited exceptions via mask licensing). There is no legitimate secondary market for TSMC allocation. If someone offers you one, treat it as a red flag.

Advanced packaging interposer with chip dies, macro

The price floor: foundry costs are passing through everywhere

TSMC's pricing power is now flowing through the entire chain: - **TSMC itself:** wafer price increases of roughly 3–6% reported from January 2027, steepest at 2nm and 3nm (unconfirmed); mature-node increases also reported (per TrendForce). - **IC designers:** Reportedly eyeing 5% to double-digit price hikes in late 2026–early 2027 as foundry costs rise (TrendForce, via Economic Daily News). - **Other foundries:** SMIC already raised prices, with utilization at 93.7% and average wafer ASP up 5.7% quarter-on-quarter (Reuters via TrendForce). Chinese foundries are also reportedly considering increases. - **12-inch wafers:** Long-term agreements reportedly up 15–40%+ for 2027. The pattern is the same as memory: the shortage has moved from a cyclical event to a structural repricing, and every layer of the chain is passing costs downstream. Buyers who waited for "normalization" have now waited through three quarters of increases.

A buyer's foundry playbook

**1. Audit your foundry exposure.** For every critical part, identify: which foundry makes it, on which node, and what your allocation tier is. If you don't know, ask your supplier. Most buyers discover their foundry exposure only when allocation gets cut. **2. Commit earlier, not later.** TSMC won't commit to 2027 capacity numbers, but your competitors are committing to TSMC. The 2nm order increases (10–20% reported) mean the queue is lengthening. If you need leading-edge capacity in 2027, the time to reserve it was last quarter; the second-best time is now. **3. Qualify a second foundry source.** Samsung Foundry (SF2P 2nm) and Intel Foundry (18A) are the alternatives. Both have real limitations (Samsung 2nm yields reported at 50–60% vs. TSMC's 70%+; Intel 18A still ramping external capacity), but a qualified second source is worth more than a 5% price saving on a single source. Start qualification now — it takes months. **4. Budget for continued increases.** Model 2027 foundry costs at +6–8% for leading edge, single-digit for mature nodes, and assume IC designers pass through 5–10%. If your product margins can't absorb that, you need a price increase, a redesign, or a different node — not hope. **5. Ask the allocation questions.** - "What is my allocation tier if demand exceeds supply?" - "Is my capacity covered by a long-term agreement, and what are its pricing terms?" - "What is my CoWoS/packaging allocation, separate from wafer allocation?" (Wafer capacity without packaging capacity is unusable.) **6. Watch the packaging bottleneck, not just wafers.** CoWoS lead times exceed 50 weeks. If your product uses advanced packaging, your constraint is packaging, not wafers. Track packaging allocation as a separate line item.

Frequently asked questions

**Does TSMC's record profit mean chip prices will keep rising?** Not directly — TSMC's profit reflects AI demand and pricing power, not a promise of future increases. But the underlying conditions (sold-out leading-edge capacity, 2nm at $30,000/water and rising, CoWoS sold out) all point to continued upward pressure on foundry costs through 2027. The profit is a symptom; the capacity constraint is the cause. **What does "no sign of slowdown" actually cover?** Wei was talking about AI accelerator demand specifically — orders from NVIDIA, AMD, hyperscalers, and custom-ASIC customers. It does not mean all chip demand is strong. Smartphone revenue share fell to 21%, and consumer markets are weakening (see our companion article on smartphone demand destruction). The strength is concentrated in AI. **Should I switch to Samsung or Intel foundry?** Only with eyes open. Samsung's 2nm yields are reported lower than TSMC's; Intel's 18A external capacity is still ramping. Both are viable second sources for qualification and risk diversification. Neither is a drop-in replacement for TSMC leading-edge capacity today. Qualify them as insurance, not as a primary switch. **Can I buy TSMC allocation on a secondary market?** TSMC reportedly says no — customers may not sublet or auction capacity. Treat any offer of "TSMC allocation" from a third party as suspect. The legitimate path is direct allocation through TSMC or through an authorized chip vendor. **What happens if AI demand does cool in 2027?** TSMC's caution on 2027 planning reflects exactly this risk. If AI demand cools, leading-edge capacity could loosen — but TSMC has ~20 fabs in various stages of construction or planning, and capacity additions take years. A demand cooldown would more likely slow the rate of price increases than reverse them. Don't plan on a price collapse. **How does this connect to the memory shortage?** Same root cause (AI demand absorbing capacity), different bottleneck. Memory is constrained by HBM wafer allocation; logic is constrained by foundry allocation and CoWoS packaging. Both point the same way: AI demand is crowding out everything else, and the crowding will persist through 2027. ---

Sources

Use the latest guidance for the exact part and manufacturer when deciding acceptance criteria.