The short version

TSMC has reportedly finalized plans to raise wafer-out prices by 3-6% from January 2027, according to Liberty Times and DIGITIMES citing supply-chain sources. TSMC has not publicly confirmed the figures. Advanced nodes (2nm, 3nm) see the steepest increases within the range. Most coverage stops at the headline number. Buyers shouldn't. The 3–6% is the *floor* of the 2027 cost reset, not the number that lands on your invoices — and the wafer hike is only one layer of a stack that includes silicon wafer prices rising sharply, substrates under long-term lock-up (#55), and memory up 30–40% in reported 2027 quotes. This article explains the pass-through chain — and why mature-node buyers, who assume "3–6% on advanced nodes" doesn't concern them, are the most exposed of all.

Silicon wafers in fab, macro

What was actually reported

The reported structure of TSMC's 2027 adjustment: - **Timing:** January 2027, applied by process node. - **Headline range:** +3–6% on wafer-out prices. - **Advanced nodes:** 2nm and 3nm at the top of the range. - **Mature/specialty nodes:** Reports say mature-node increases vary by product and customer, up to about 10% (Nikkei). - **Confirmation status:** Notifications to customers are reported by multiple supply-chain sources (Liberty Times and DIGITIMES, relayed by TrendForce); the notifications themselves have not been independently verified, and TSMC does not comment on pricing details, describing its pricing only as aligned with long-term strategy. The operating backdrop explains the confidence: 8-inch capacity across the TSMC-linked ecosystem is tight (Vanguard guided about 90% utilization in Q3, expected to rise in Q4), and CoWoS advanced packaging remains tight in the October reporting. As Chairman C.C. Wei has put it, choosing a foundry partner is not like buying milk at a convenience store — dissatisfied today, switch tomorrow. Customers facing the increase cannot quickly move: as Wei has put it, choosing a technology and ramping it 'takes about five years' — his estimate for a technology partnership, not a per-product guarantee.

Semiconductor fab cleanroom corridor

Why 3–6% is the floor, not your number

**1. The range is a base, and mix does the rest.** The wafer-out figure is the starting adjustment on the foundry's price list. What a chip designer actually pays depends on node, volume tier, packaging (CoWoS carries its own scarcity premium), and rush terms. Our own read of the same reports: the 3–6% functions as a *price floor* — AI orders, priced through the full stack of advanced nodes plus packaging, can pay multiples of the headline. **2. Other foundries are moving the same way.** Samsung Foundry has reportedly raised prices too — TrendForce (citing Reuters) reported increases of 10–15% on SF4 for US and Chinese customers (5–10% for Taiwan) and 10–15% on SF5. Vanguard — the TSMC-linked 8-inch specialist — expects 2027 price increases no smaller than 2026's (its chairman, via CNA reporting relayed by TrendForce). When the price-setter moves, the reference price moves for the whole industry. **3. The input stack is rising underneath.** Beneath the foundry sits the silicon wafer itself: Commercial Times reports 2027 long-term agreement prices for 12-inch wafers could rise 15-25% for epitaxial wafers and more than 40% for polished wafers, with some second-tier customers over 50%; spot prices are expected to exceed LTA levels as early as Q4. The pressure persists because AI memory is wafer-hungry: Micron has put HBM at about three times the wafer capacity of conventional DRAM per bit (its HBM3E-versus-DDR5 comparison, covered in our SK hynix guide). Add substrates (#55: Samsung Electro-Mechanics' KRW 6.78 trillion FC-BGA expansion, with Sejong mass production targeted for September 2028 and unnamed big-tech customers providing funding support) and packaging, and the foundry's 3–6% is one layer in a stack that compounds. **4. Your supplier's hike will likely be bigger than TSMC's.** Chip designers facing +3–6% on wafers, +15–25% on wafer LTAs underneath, plus substrate, packaging, and test inflation do not pass through +3–6%. They reprice their catalogs. Power, driver and MCU suppliers are reportedly weighing increases from 5% to double digits (TrendForce, citing Economic Daily News), because suppliers rebuild margin on the new cost base and price scarce allocation at what the market bears.

Stacked silicon wafers close-up

The mature-node trap: why MCU and PMIC buyers are most exposed

Read the announcement again: advanced nodes get a published range; **mature and specialty nodes are "individual negotiation."** That phrase should worry every buyer of MCUs, PMICs, drivers, and analog parts — the catalog this site sells. - Tight 8-inch utilization across the ecosystem means mature capacity is rationed, not discounted. In individual negotiation, the customers with volume and history are positioned for the low end; smaller buyers should expect the high end — or an allocation cut. - AI data centers are pulling mature-node demand too: every AI server needs PMICs, MCUs, MOSFETs, drivers, sensors, and mixed-signal parts in quantity. Vanguard guided 8-inch utilization of about 90% in Q3, expected to rise in Q4 (company guidance via CNA, relayed by TrendForce) — demand it links to exactly this AI-server spillover. - Mature-node chip prices have the least pass-through room at the *end customer* (competitive consumer/industrial markets), which makes designers squeeze — or exit — low-margin parts. The practical risk for buyers is not just price: it is NRND notices and quiet line closures on the parts nobody repriced profitably. Apple's reported position shows the stack from the top: it has reportedly accepted Samsung's Q1 2027 memory quotes at +30–40% over Q3 2026 levels (a single reporting chain, unconfirmed) *and* faces the TSMC wafer increase on its A/M-series chips. If the world's most powerful buyer pays both, plan on paying yours.

Microcontroller chips on board macro

What this means for component buyers

**1. Rebuild your 2027 BOM cost model now.** Do not carry 2026 prices into 2027 quotes. Working assumptions (our budgeting scenarios, not forecasts): foundry-driven parts +5–15% (mature) to +10–20% (advanced-adjacent), memory +30–40% at contract reset, passives per #57. Long-cycle orders priced on 2026 assumptions are margin losses waiting to ship. **2. Use the Q4 negotiation window.** 2027 pricing is being set in this quarter's contract rounds — TSMC's notifications are reported to be out, Samsung's memory quotes are reportedly being accepted, SEMCO's Q4 MLCC round is announced. Every week you wait, more of the 2027 stack is locked at the new level without your input. Bring volume commitments and term length; in a rationed market those — not price pressure — are what buy you the low end of the range. **3. Split your book: LTA the stable, spot the flexible.** Parts with >18-month lifecycle and stable volumes belong in LTAs at the new base (the silicon-wafer market shows the value: 2027 LTA prices could rise 15–25% for epitaxial wafers and more than 40% for polished wafers). Keep flexibility only where your demand is genuinely uncertain. **4. Watch the mature-node tail risk.** For every critical MCU/PMIC/analog part, confirm its foundry and node, check the maker's 2027 pricing posture, and qualify a second source *before* an NRND or allocation letter forces the timeline. Pin-compatible alternatives qualified in calm quarters are cheap insurance. **5. Don't expect switching to save you.** Samsung, VIS and others are raising into the same demand. Second sources are for allocation security and negotiation credibility (#56's lesson), not for escaping the cycle. Budget the cycle; negotiate your position within it. The parts in our catalog sit directly in this chain: mainstream MCUs like the GD32 and STM32 families and the PMICs around them are built on exactly the mature and specialty nodes now under individual negotiation amid tight 8-inch capacity. Their 2027 prices will be set in the rounds happening now. Send us your 2027 BOM and we'll flag which lines carry foundry pass-through risk and which to lock first.

Frequently asked questions

**Has TSMC officially confirmed the 3–6% increase?** No. Notifications have been reported by DIGITIMES and multiple supply-chain reports; TSMC's public position is its standing one — no comment on pricing details. Treat the range as a reported notification, not an official announcement. **Why is the headline range not the number on my invoice?** The 3–6% is the foundry's reported wafer-out list adjustment. What lands on a chip price depends on node mix, packaging (CoWoS carries its own reported premium), and how each designer rebuilds margin on the new cost base — which is why this guide treats the range as a floor for budgeting, not a quote. **I'm a small buyer of mature-node parts. Does this affect me?** Most of all. Mature nodes are individually negotiated while 8-inch capacity is tight — small buyers have the least leverage and should expect the highest end of increases, allocation risk, and NRND tail risk. Your designer's repricing, not TSMC's headline, is your number. **When will the increases reach distributor pricing?** Through 2027 contract resets: memory quotes already reset for Q1 2027 (+30–40% reported), foundry adjustments apply from January, and catalog repricing typically follows within one to two quarters. Spot prices move first; contract prices ratchet at renewal. **Should I stockpile ahead of January?** Selectively. Stockpiling everything ties up cash in parts whose finished-price elasticity is lower than the wafer's. Prioritize long-lead, hard-to-substitute, allocation-exposed parts; negotiate LTAs for the rest. (Samsung's August MLCC hike showed how panic stockpiling amplifies the next round — #57.) **Will prices come back down in 2028?** New capacity lands from 2028 (SEMCO substrates September 2028; CXMT DRAM scale; TSMC's own expansions), but supply additions face ~3-year decision-to-production lags and AI demand keeps absorbing output. Our planning stance is a higher cost plateau, not a return to 2025 pricing — a judgment, not a dated forecast. ---

Sources

Use the latest guidance for the exact part and manufacturer when deciding acceptance criteria.