DRAM Roadmap Fork: Micron 3D vs 4F² — Buyer Guide

The short version

The next decade of DRAM economics is being decided this month, in public, and the three incumbents have chosen different roads. At an October 21 technology webinar, Micron unveiled a 10-year roadmap that pointedly **excludes 4F²** — the denser cell architecture CXMT is about to ship in server modules (#61). Micron's technology chief Scott DeBoer said Micron has studied 4F² for more than 20 years but will not commercialise it, citing process complexity, higher cost and fundamental scaling limits. Micron will instead keep scaling today's 6F² cells (its 1δ generation is expected to enter mass production in late 2027) and go straight to **3D DRAM** — stacking cells vertically, as NAND did a decade ago. Samsung and SK hynix are doing the opposite of choosing: both are developing 4F² *and* 3D DRAM in parallel, paying double R&D to keep both options alive. And CXMT — restricted from EUV tools by export controls — is pushing 4F² to market first, and has said it will launch 4F² server DDR5 RDIMMs by year-end. For buyers, the fork matters because the 2028–29 cost curve (#61: peak, then a forecast −23%) is not a law of nature — its slope depends on which of these bets yields. This article maps the three positions and what each outcome does to your future sourcing.

The three positions

**Micron: skip 4F², scale 6F², then jump to 3D.** The detail from the webinar (via Business Korea, October 26): after the currently produced 1γ generation, Micron's **1δ process is expected to enter mass production in H2 2027**, with targeted bit-density gains in the mid-20% range — conventional scaling still has a solid generation left. Beyond that: wafer bonding and next-generation EUV to keep squeezing 6F², and long-term, 3D DRAM that stacks cells vertically like floors in a building. Micron will time 3D's introduction by manufacturing cost and process difficulty, not by announcement value. DeBoer's 4F² verdict is the sharpest on record from an incumbent: two decades of study, implementable in principle, uneconomic in practice — smaller cells demand capacitor spacing that fights the shrink, complexity climbs, and yield pays the bill. **Samsung & SK hynix: two-track hedge.** Samsung is developing 4F² using vertical channel transistors (VCT) — standing the transistor upright to cut cell area — as DS division CTO Song Jae-hyuk confirmed at SEDEX 2026 on October 14, alongside 3D DRAM work. SK hynix is developing 4F² based on vertical-gate technology and also researching 3D DRAM. The hedge's logic: if 4F² yields, they extend planar economics; if it doesn't, 3D is warm. The hedge's cost: every new cell structure requires co-developing equipment, materials, and design with the supply chain — running two such programs roughly doubles that co-development burden — our characterization, not a figure either company has published. Korea is paying an insurance premium Micron declined. **CXMT: 4F² under an EUV restriction.** CXMT is restricted from EUV tools by export controls and has said it will launch 4F² server DDR5 RDIMMs by year-end; analysts have not confirmed that one drives the other. A 4F² server DDR5 module by year-end would prove the structure shippable. But shipping a product and leapfrogging incumbents are different events: performance, power, and above all **yield** — the share of good dies per wafer — remain undisclosed and unverified. In memory, competitiveness *is* mass-production cost: a smaller cell with a complex process and weak yield produces a *more* expensive bit, not a cheaper one.

Why yield, not geometry, decides your 2029 price

The physics every buyer should hold onto: 4F² cuts theoretical cell area by ~33% (from 3F×2F to 2F×2F). That is a geometry claim. Your price is set by a different variable — cost per good bit, which is geometry divided by yield and multiplied by process cost. A 33% smaller cell at 15% lower yield and 20% higher process cost is a price *increase* wearing a breakthrough's clothes. That is why three sophisticated companies, looking at the same physics, reached different strategies — they disagree about the yield trajectory, not the diagram. And it is why the 2028 forecasts in #61 carry a technology caveat: the models assume conventional capacity additions. A genuine 4F² yield breakthrough (by CXMT or Korea) steepens the post-peak decline; a 4F² failure across the industry (Micron's prediction) makes the plateau higher and longer; a 3D DRAM surprise reshuffles everything again — for whichever vendor lands it first.

What this means for component buyers

**1. Qualify across the fork, not along one road.** For DRAM-dependent products with lifecycles reaching 2028–29, your approved-vendor strategy should span the strategies: a two-track Korean maker, Micron's scale-then-3D path, and CXMT as a monitored challenger. The 2029 cost leader is genuinely unknowable today; a vendor list that only contains one roadmap is a bet, not a plan. **2. Grade roadmap claims by yield evidence, not launch dates.** CXMT's module launch will generate "breakthrough" coverage. Hold your qualification bar where it belongs: disclosed yields, sustained volumes, server-customer field data. The same applies to any vendor's 3D DRAM timeline — Micron itself says it will introduce 3D when cost and difficulty say so, which is the honest template for reading everyone's announcements. **3. Anchor near-term plans to the one dated expectation: 1δ in H2 2027.** Whatever the fork's outcome, conventional scaling is expected to deliver one more step — targeted mid-20% density gains in late 2027 — that supports the supply models behind the 2028 peak forecast. Plans for 2027–28 can reasonably plan around that step as the base case: it is a roadmap expectation from the incumbent (TrendForce reports 1δ *expected* to enter mass production in H2 2027), not a shipped product. Plans that assume an *additional* 4F²-driven cost collapse by 2028 are stacking speculation on a forecast. **4. Put technology triggers in the watch list next to the price triggers.** #61 listed four cycle triggers (CXMT yields, Korean fab ramps, capex, LTA coverage). The fork adds three: CXMT's first verified 4F² yield/volume data; any Korean decision to *drop* one track (a dropped 4F² program validates Micron); and 3D DRAM sampling from any maker. Each reprices 2029 supply expectations before it touches a contract. **5. Don't let EUV logic mislead your China sourcing.** CXMT's 4F² push comes alongside its EUV restriction — clever, and possibly effective. But that doesn't repeal #59/#61's constraints: CXMT's own IPO prospectus says its supply capacity falls far short of Chinese domestic demand (per XenoSpectrum's reading of the prospectus), and export buyers should model CXMT as an option that matures, not a supply that exists, until volumes and yields are proven at server grade. The DRAM lines in our catalog sit on both sides of the fork — Samsung's DDR4 K4A8G165WC-BCTD from the two-track camp and Micron's MT41K128M16JT-125 from the scale-and-3D camp. Send us your DRAM requirements through 2029 and we'll map them against the fork: what's safely single-sourced today, where a second roadmap should be qualified, and which trigger events should reopen the plan.

Frequently asked questions

**What is 4F², in plain terms?** DRAM stores each bit in a cell — a capacitor plus a transistor. In today's 6F² layout a cell occupies 3 units by 2 units of area (F = minimum feature size). 4F² rearranges it to 2 by 2, theoretically shrinking cell area ~33% and fitting more bits per wafer. The catch is manufacturing: capacitors still need spacing, the process grows more complex, and yield can eat the gain. **Why would Micron reject a technology it studied for 20 years?** Precisely *because* it studied it for 20 years. Its CTPO's position: the structure is implementable but offers no sustainable scaling path — process complexity and cost cap the benefit. Micron is betting its R&D on milking 6F² (1δ in 2027) and then jumping straight to vertical 3D DRAM, the path NAND already proved. **Does Samsung/SK hynix's two-track approach mean 4F² will win?** No — it means they can afford to insure against both outcomes. Running two cell-structure programs means paying for equipment, materials and design co-development on two tracks at once — a heavy duplication of effort, in our characterization. It's an option purchase, not a prediction. Watch for either company quietly dropping a track; that's the informative event. **If CXMT ships 4F² servers this year, is it suddenly level with Korea?** Not on the evidence available. A launch proves a product exists; competitiveness requires disclosed yield, cost per bit, power, and sustained volume — none yet public. Korean and US incumbents also hold the EUV roadmap CXMT can't access. CXMT's progress is real and worth monitoring; it is not yet a supply fact for export buyers. **What is 3D DRAM and when does it arrive?** Instead of shrinking cells on a plane, 3D DRAM stacks them vertically — the transition NAND flash made years ago, but harder for DRAM's structure. No incumbent has committed to a production date; Micron explicitly ties timing to cost and process difficulty. Treat any 3D DRAM date in a sales deck as aspirational until sampling with data appears. **How does this change the 2028 peak forecast (#61)?** It adds variance around it. The base case (conventional capacity + 1δ) still has prices turning in 2028 on current forecasts. A 4F² breakthrough steepens the decline; a collective 4F² failure flattens it into a higher, longer plateau; and the 2029 "red ocean" scenario leans partly on new *conventional* capacity that is already being built — that part doesn't depend on the fork at all. ---

Sources

Use the latest guidance for the exact part and manufacturer when deciding acceptance criteria.